Semiconductor integrated circuits (IC) and their manufacturing techniques are well known in the art. In typical integrated circuits, a large number of semiconductor devices are fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors or interconnects are typically employed for coupling selected devices together. In some integrated circuits, some of the conductive links may be coupled to fuses which may be selectively programmed (i.e. blown) after fabrication using lasers. By way of example, in a logic integrated circuit, fuses may be employed during manufacturing to protect from destruction some of the gate stacks of the transistors from inadvertent built-up of electrostatic charge. Once the fabrication of the IC is substantially complete, the fuses may be blown or cut to permit the logic circuit to function as if the protective current paths never existed. More commonly, fuses may be employed for repairing defects found in the logic circuit by appropriate replacement of defective elements with redundancy replacement elements present within or without the chip.
Fuses may be selectively blown or programmed with a laser beam. Once blown, the fuse changes from a highly conductive state to a highly resistive state (i.e. non-conductive) which inhibits current from flowing through it and represents an open circuit to the path taken by the current. Typically, a fuse is formed of a metallic material and the laser beam imparts enough energy into the fuse to melt the metal. The fuse is formed in a dielectric material such as silicon oxide and a silicon oxide dielectric layer formed over the fuse. Energy delivered from the laser is absorbed by the surrounding silicon oxide dielectric layers. Since silicon oxide is a relatively “rigid” material, the fuse can be blown with minimal damage to the surrounding dielectric layers. Thus, the risk of incorrectly programming one fuse when programming another nearby fuse is relatively low. FIG. 1 shows fuses 10A-C formed in a silicon oxide dielectric layer 15. Fuse 10A has been “blown” open by a laser (not shown). It is noted that there is minimal damage 16 of the silicon oxide dielectric layer 15 such that adjacent fuses 10A and 10C are not adversely affected by the blowing of fuse 10B.
A trend in the fabrication of integrated circuits is the use of “low-k” dielectric material in an inter-level dielectric layer to reduce parasitic capacitance between interconnects (e.g. wires and vias) resulting in an increase in the speed of devices. Fuses are typically formed in the same inter-level dielectric layer as the interconnects. The use of low-k dielectrics in the back-end-of-line (BEOL) levels can result in a reduction in the material strength of the inter-level dielectric layer. For example, having layers of silicon oxide dielectric (e.g. a rigid material) and low-k dielectric (e.g. a non-rigid material) formed upon each other have resulted in separation of the different material layers when placed under a physical stress. The separation of the inter-level dielectric layers can result in yield or reliability issues due to, for example, exposure of interconnects to air (e.g. corrosion of metal interconnects). Since fuses are formed in the same inter-level dielectric layer as interconnects, fuses are also susceptible to damage.
Thus, fuses formed in a low-k dielectric layer having spacing consistent with conventional silicon oxide fuse integration and high reliability/yield are desired.